[ Pobierz całość w formacie PDF ]
.54 Chapter 2 X86 Processor Architecture2.3 Control UnitThe control unit, or control store, is part of the CPU and contains the microprogram,also referred to as microcode.The microprogram is stored in a high-speed memoryand accommodates a set of low-level instructions that control the machine s hardwareand is machine dependent; that is, it is written for a particular type computer.Theinstructions in a microprogram represent micro operations that the CPU performs toexecute a machine-language instruction.A microprogram is also referred to as firm-ware.A control word in the microprogram is normally a very-long instruction word(VLIW)  ten bytes or more  to perform the many micro operations required by aCPU instruction, such as effective address generation and load/reset registers.Thereare two types of control units: hardwired and microprogrammed.A Hardwired con-trol unit is too complex for large machines and is inherently inflexible to changesrequired by design changes or modification of the instruction set.A micropro-grammed control unit does not have the limitations of a hardwired controller  tochange the firmware, simply change the program that resides in a programmable read-only memory (PROM).Figure 2.4 shows the organization of a general micropro-grammed control unit.Instruction registerCondition codesAddress generationMicroprogram counter clockMicroprogram counter>MicroprogramControl storage.Control wordControl word clockregister>(¼ instruction).EAXin BLinBranchEAXout BLoutaddressFigure 2.4 Organization of a general microprogrammed control unit.2.4 Memory Unit 55The instruction register contains the current instruction.The address generationblock is set to the starting address of the microprogram for a particular instruction andis a function of the contents of the instruction register, the condition codes, and thebranch address of the current control word (microinstruction).The microprogramcounter is similar to the program counter (PC) of a computer  it points to the addressof the next instruction.The microprogram counter is incremented by 1 or set to thebranch address.The control storage block is a PROM that contains the microprogram(or firmware).The control word register contains the current microinstruction to control themachine s hardware for a specific macroinstruction.Microinstructions are fetchedfrom control storage in a similar manner to instructions fetched from main memory.Amicroinstruction has two main parts: a control field and an address field.The controlfield issues control lines, such as EAXin, which loads the EAX register with data at thenext active clock transition; and EAXout, which gates the contents of EAX to the des-tination bus.The address field (branch address) indicates the address of the nextmicroinstruction in the microprogram if a branch is required.It is desirable to keep the control word as short as possible to minimize the hard-ware and yet have as many unique individual bits as possible to obtain high-speed exe-cution of the macro instructions.Microinstructions (control words) are generallyclassifies as a horizontal format, a vertical format, or a combination format, which isa combination of vertical and horizontal formats.The horizontal format has no decoding; therefore, it has very long formats.Thisprovides high operating speeds with a high degree of parallelism.An example of thehorizontal format is shown in Figure 2.5(a).The vertical format has a large amount ofdecoding; therefore, it has short formats.It operates at a slower speed due to the inclu-sion of a decoder and is not highly parallel.An example of the vertical format isshown in Figure 2.5(b).Most microprogrammed computers use a combination of hor-izontal and vertical formats.An example of the combination format is shown in Fig-ure 2.5(c).Note that decoder output 0 cannot be used, because the field being decodedmay be all zeroes.2.4 Memory UnitThe memory unit consists primarily of main memory and cache.It also contains tworegisters: memory address register and memory data register.The memory addressregister (MAR) contains the memory address to which data are written of from whichdata are read.The memory data register (MDR) contains the data that is written tomemory or read from memory.2.4.1 Main MemoryThe main memory, also called random access memory (RAM), contains the instruc-tions and data for the computer.There are typically two types RAM: static RAM and56 Chapter 2 X86 Processor Architecturedynamic RAM.Static RAM is designed using flip-flops that store one bit of informa-tion.A static RAM does not need refreshing and operates at a higher speed thandynamic RAM, but requires more hardware.Dynamic RAM stores one bit of infor-mation in a capacitor and associated hardware.Since the charge in the capacitor leaksand diminishes with time, the charge must be refreshed periodically in order to main-tain the state of the data.The density of a dynamic RAM is much greater than the den-sity of a static RAM, but operates at a slower speed.n bit control field.n 1 n 2 1 0.(a)One control fieldDecoder0 1 2.n 1(b)Control fields.Decoder Decoder0 1.7 0 1.14 15(c)Figure 2.5 Examples of microinstruction formats: (a) horizontal; (b) vertical;and (c) combination.2.4.2 Hamming CodeErrors can occur in the transmission or storage of information being sent to or frommemory.A typical error detection and correction scheme is one developed by RichardW.Hamming.The basic Hamming code can detect single or double errors and cancorrect single errors.The information sent to memory is coded in the form shown in2.4 Memory Unit 57Figure 2.6.A code word contains n bits consisting of m message bits plus k paritycheck bits.The m bits represent the information or message part of the code word; thek bits are used for detecting and correcting errors, where k = n  m.Since there can be an error in any bit position, including the parity check bits, theremust be a sufficient number of k parity check bits to identify any of the m + k bitpositions.The parity check bits are normally embedded in the code word and arepositioned in columns with column numbers that are a power of two, as shown in Fig-ure 2.7 for a code word containing four message bits (m3, m5, m6, m7) and three paritybits ( p1, p2, p4).Code word (n bits)Message word Parity check word(m bits) (k bits)m1, m2, Å" Å" Å" Å" Å" Å" Å" Å" Å" , mm p1, p2, Å" Å" Å" , pkCode word X = x1, x2, Å" Å" Å" Å" Å" Å" Å" Å" Å" , xm, xm + 1, Å" Å" Å" , xnFigure 2.6 Code word to encode message bits using the Hamming code.Column number 1 2 3 4 5 6 7Code word = p1 p2 m3 p4 m5 m6 m7Figure 2 [ Pobierz caÅ‚ość w formacie PDF ]